1. Field of the Invention
This invention relates to semiconductor devices and more particularly to CMOS circuits.
2. Description of Related Art
The design trade-off between low-power and signal strength in dynamic and analog circuits usually determines the selection of threshold voltage Vth in the CMOS technology. However, the threshold voltage Vth is not easily scalable with the continuous voltage and geometrical scaling in CMOS transistor technology.
Source/drain asymmetry effects in charge pumps embodied with CMOS transistors have been discussed in the literature, but all previous work has focused on the comparison with the symmetrical devices in the forward biasing directions. Parasitic RC elements and carrier transport in tailored channel electric fields have been studied. None of the previous work has proposed to use both biasing directions to achieve better dynamic and analog circuit design.
U.S. Pat. No. 4,439,692 of Beekmans et al. for xe2x80x9cFeedback-Controlled Substrate Bias Generatorxe2x80x9d describes a charge pump with three diodes connected in series and a pair of capacitors which have one plate connected to the junctions between the diodes. The other plate of each capacitor is connected to voltage sources which alternate between high and low values with one voltage always being high when other voltage is low.
U.S. Pat. No. 5,081,371 of Wong for xe2x80x9cIntegrated Charge Pump Circuit with Back Bias Voltage Reductionxe2x80x9d shows a charge pump with three NMOS transistors connected in a series by source to diode connections. The NMOS transistors which are connected as diodes with the gate shorted to the drain. There are three capacitors connected to the sources of the transistor with the two intermediate capacitors connected to clock signals which are 180xc2x0 out of phase with each other as provided by inverter circuits driven by a common clock.
U.S. Pat. No. 5,386,151 of Folmsbee for xe2x80x9cLow Voltage Charge Pumps Using P-Well Driven MOS Capacitorsxe2x80x9d describes the operation of a charge pump formed by diode connected nMOS FET devices with the gate shorted to the drain and MOS capacitors formed with a p-well acting as one plate thereof.
U.S. Pat. No. 5,589,697 of Smayling et al. for xe2x80x9cCharge Pump Circuit with Capacitorsxe2x80x9d shows a series of Schottky diodes with one plate of a separate capacitor connected to the cathode of each of the diodes. The other plates of the capacitors are connected to alternate phase clock pulses generated by clock circuitry.
U.S. Pat. No. 5,524,266 of Tedrow et al. for xe2x80x9cSystem Having Multiple Phase Boosted Charge Pumps with a Plurality of Stagesxe2x80x9d shows a charge pump circuit in which each stage includes a storage capacitor plus two FET devices which include a switching transistor and a control transistor. Either four or two different clock signals are employed in the embodiments shown.
U.S. Pat. No. 5,943,271 of Fujita for xe2x80x9cSemiconductor Integrated Circuit Devicexe2x80x9d shows a modified Dickson type pMOS FET charge pump circuit with two clocks with different phases devices to bias a semiconductor substrate or a well.
Wu et al. xe2x80x9cMOS Charge Pumps for Low-Voltage Operationxe2x80x9d describes a traditional Dickson four stage charge pump in which MOSFET devices are connected as diodes, so that the charge thereon can be pumped. The paper describes other charge pumps for low-voltage operation, greater pumping gains, and higher output voltages that a Dickson charge pump. A first embodiment comprises a four-stage charge pump with static charge transfer switch (CTS) stages. Each stage includes at least two MOS devices connected in parallel. For each stage, in addition to the usual diode connected MOSFET transistor, there is a charge transfer switch (CTS) transistor connected in parallel with the diode connected transistor. The CTS transistors have their gate electrodes connected to the output of the next stage of the four-stage device. There is also a dynamic CTS transistor embodiment in which each CTS is controlled by a pair of pass transistors.
U.S. Pat. No. 6,191,963 of McPartland et al. for xe2x80x9cCharge Pump with No Diode Drop at Output Stagexe2x80x9d describes a charge pump with a series of stages with each stage including a transistor, a diode connected transistor, and a capacitor with the transistor and the diode connected transistor forming a charge transfer switch. The switches are controlled by alternately by inverted clock signals.
Charge pump circuits can boost the voltage on the wordlines (WL) of SRAM/DRAM devices, and provide large write/erase voltages for EEPROM and/or FLASH devices. For System-on-Chip (SoC) applications integrating various functional components with different voltage scaling, voltage multiplication is essential. Due to requirements for low-power, charge pumps need to be efficient in terms of power conversion and voltage multiplication. Conventional charge pumps and voltage multipliers are implemented by one-direction switches to push charges to a storage capacitor in a Dickson type charge pump circuit which is described in Wu et al. above.
FIG. 3 shows a prior art Dickson type of MOSFET charge pump circuit which can generate a voltage higher than a source voltage Vdd. The charge pump circuit of FIG. 3 consists of N-MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) M0 to M4 connected in series with each MOSFET transistor connected as a diode by having its gate and drain connected/short circuited together at nodes N0-N4. Each of a set of charge pump capacitors C1-C4 has one of its two terminals connected to the respective junction N1-N4 of the gates and drains of the MOSFETs M1-M4, as well as, being connected to the sources of MOSFETs M0-M3. A fifth capacitor Cf is connected to the source electrode of the FET M4.
FIG. 3 also shows the input waveforms of clocks xcfx861 and xcfx862. The two clock inputs are operated 180xc2x0 out of phase with respect to each other and are alternately applied to the other ends of the capacitors C1-4 with the capacitors C1 and C3 connected through node N6 to clock line xcfx861 and the capacitors C2 and C4 connected through node N7 to clock line xcfx862.
The drain and gate of the MOSFET M1 are connected to the source voltage Vdd via an N-MOS FET M0. The source of the FET M4 serves to provide the output voltage of the circuit. When the voltage on the node N1 increases, the first FET M0 can prevent a charge from migrating from the junction N1 to the source voltage Vdd.
Principle of Operation of a Dickson Charge Pump Circuit
Referring to FIG. 3, assume that the threshold voltage of the n-MOSFET M0 is Vt0, and that initially the clock xcfx861 is at a low level 0V). Then, the potential of the junction (or terminal) N1 is (Vddxe2x88x92Vt0). When the clock xcfx861 is switched to a high level at time t1, a potential at the junction N1 can be expressed by the following equation:
(Vddxe2x88x92Vt0)+Vxcfx861(C1/(C1+C1S))xe2x80x83xe2x80x83Eq.(1)
where Vxcfx861 is the voltage amplitude of the clock xcfx861, and C1S is the parasitic capacitance (not shown in the figure).
At this point, the clock xcfx862 is at a low level (0V), but the potential on the junction N2 is raised by the flow of charge (filling) the capacitor C2 by discharging (emptying) charge Q1 from the capacitor C1. The charge Q1 migrates (is pumped) from the junction N1 through to the junction N2 into capacitor C2 and increases the potential of the junction N2. The maximum potential of junction N2 can be expressed as:
(Vddxe2x88x92Vt0)+Vxcfx861(C1/(C1+C1S))xe2x88x92Vt1xe2x80x83xe2x80x83Eq.(2)
where Vt1 is the threshold voltage of the MOSFET M1.
Thus, it can be shown that the circuit can boost the voltage by the increment Vxcfx86(C/(C+CS))xe2x88x92Vt at each pumping stage.
The potential of the junction N1 is lowered when the clock xcfx861 is switched to a low level (0V). At the same time, a charge corresponding to the charge Q1 is fed from the power source Vdd to the junction N1 via the MOSFET M0, thereby setting up a potential of (Vddxe2x88x92Vt0). Similarly, the potential of the junction N2 is raised when the clock xcfx862 is switched to a high level. Thus, a charge of Q2 migrates (is pumped) from the junction N2 to a junction N3 and boosts the potential of the junction N3 by charging (filling) the capacitor C3.
In this manner, charge is pumped sequentially (analogously to a bucket brigade) from the MOSFET M1 to the MOSFET M2, then to the MOSFET M3, and then to the MOSFET M4. Finally, a high voltage appears on the output node, Vout. The maximum output voltage, V max, available with this circuit can be expressed as:
Vmax=(Vddxe2x88x92Vt0)+N[Vxcfx861C/(C+CS)xe2x88x92Vt]xe2x80x83xe2x80x83Eq.(3)
where
N=number of stages of the circuit.
V100=amplitude of the clocks xcfx861 and xcfx862 
C=capacitance of the capacitors C1-C4 
CS=stray (parasitic) capacitance of MOSFETs M1-M4
Vt=threshold voltage of the MOSFETs M1-M4
Note that in the case of FIG. 3, since there are four stages N=4.
The efficiency of a charge pump circuit is limited by the ratio between the storage capacitance C and the stray capacitance CS on the switching node (charge sharing) and by the energy loss on generation of control clock signals. Since the clock frequency will in general increase the pumping efficiency, but simultaneously increase energy used in clock generation, an optimal design may be determined from careful analysis. The voltage gain at each stage in the conventional design is as follows:                     DV        =                                            V              f                        ⁢                          C                              C                +                                  C                  s                                                              -                                    I              0                                      f              ·                              (                                  C                  +                                      C                    s                                                  )                                                                        (Eq.  4)            
where
f=clock frequency and
I0=the output current loading.
For multi-stage charge pumps to be functional, xcex94V needs to be larger than Vth of the switch for Dickson""s pass-transistor design, and larger than Vth/2 for full transmission-gate design. This poses a device design challenge on the choice of Vth of the switching transistor. There is a problem with the above design which comprises the dilemma that a lower Vth will cause more leakage currents, but that a higher Vth will pose a lower bound for the values of storage capacitance (C) and clock frequency (f).
U.S. Pat. No. 5,790,452 of Lien for xe2x80x9cMemory Cell Having Asymmetrical Source/Drain Pass Transistors and Method for Operating the Samexe2x80x9d shows a 4T (Four Transistor) SRAM (Static Random Access Memory) device with asymmetrical pass transistors and symmetrical pull down transistors.
In the Halo embodiments of the Lien patent, the asymmetric pass transistors include a P-type Halo Source (HS) region between the channel and the source region. In the Halo/GOLD (Gate Overlapped Lightly Doped drain) embodiment, between the drain region and the channel, an N type (GOLD) region was formed by a Large Angle of Tilt (LAT) ion implantation. The HS region was also formed by a LAT ion implantation process. In a variation of the Halo embodiments, the Halo region remains and if it provides the required asymmetric threshold voltage characteristics, then the GOLD region can be eliminated which provides a source region, a drain region, and a halo region adjacent to the source region without any lightly doped regions at all.
In still another case described in Lien, the asymmetrical pass transistors included a P-type interstitial gradient region is formed between the source and the channel region of an NFET device. An interstitial region, near the oxide-silicon interface at the source side of a MOSFET device can be created by damage induced by high energy, high dose N+ ion implantation. The interstitial region can attract boron to pile up at the interface. This boron pile up results in higher threshold voltages at the source side as compared to the local threshold voltage at the drain. This is by definition an asymmetric MOS FET device, but this type of device does not include any halo implant which is critical for contemporary and future CMOS technology to reduce the short channel effect.
In either case, the channel region of the NMOS devices are not indicated to have any difference in doping from the bulk of the Pxe2x88x92 monocrystalline semiconductor substrate.
In accordance with this invention, a charge pump comprises first and second clocks having a phase differential; a plurality of stages of each comprising an asymmetric FET transistor with substantially different forward and reverse threshold voltages and a capacitor. Each stage includes an asymmetric FET transistor which includes a semiconductor substrate with a channel, a drain region and a source region. The drain region is connected to a drain electrode, the source region is connected to a source electrode, and a gate electrode stack comprises a silicon oxide layer and a gate electrode formed above the channel. The drain electrode is electrically connected through an input node to the gate electrode of the FET transistor and the source electrode of each stage is connected to an output node. The capacitor of each stage has a first capacitor plate and a second capacitor plate. The first capacitor plate is connected to the source electrode of that stage. The stages are connected in series with the source electrode and the first capacitor plate of a preceding stage is connected to the input node of a succeeding stage, and the second plates of the capacitors are coupled alternately along the sequence of stages to the first clock and the second clock.
Preferably the asymmetric FET transistor has a source region halo implant; which is preferably a source region super halo implant.
Preferably, the source region super halo implant has a shallow counterdoped portion of the channel.
Preferably, the asymmetric FET transistor has a source region super halo implant with a shallow counterdoped portion of the channel and source and drain extensions adjacent to the channel between the source region and the drain region.
Preferably there is an abrupt halo contour resulting from a single RTA cycle.
Further in accordance with this invention, a semiconductor integrated charge pump circuit is driven on the basis at least two clocks in which for each positive integer xe2x80x9cixe2x80x9d from 1 to nxe2x88x921, the ith stage of the charge pump circuit is caused to have a structure in which it has large current drivability, but lower maximum arrival voltage as compared to the (i+1)-th stage of the charge pump circuit, and each stage includes an asymmetric MOSFET device connected to an alternate one of the clocks through the capacitor associated therewith.
Preferably, the asymmetric FET transistor has a source region halo implant which is preferably a super halo implant. Preferably, the asymmetric FET transistor has a source region super halo implant with a shallow counterdoped portion of the channel and source and drain extensions adjacent to the channel between the source region and the drain region with an abrupt halo contour resulting from a single RTA cycle.
Still further in accordance with this invention a semiconductor integrated charge pump circuit comprises a plurality (n) of charge pump stages (1,2,3,4 . . . n) from a first (1th) to a last (nth) stage connected in series comprising odd numbered stages (1, 3, . . . ) and even numbered stages (2, 4, . . . ); a pair of clock pulse lines, including a first clock pulse line and a second clock pulse line; the first clock pulse line connected to the odd numbered stages (1, 3, . . . ) of the charge pump stages; the second clock pulse line connected to the even numbered stages (2, 4, . . . ) of the charge pump stages; each stage including an MOSFET transistor including a source, a drain and a gate electrode with the source connected to the drain and a capacitor connected to the source, and each of the MOSFET transistors comprising an asymmetric transistor with a forward threshold voltage (VthF) and with a reverse threshold voltage (VthR), with the forward threshold voltage VthF is substantially larger than the reverse threshold voltage VthR.
Preferably, the asymmetric FET transistor has a source region halo implant which is preferably, a super halo implant preferably with a shallow counterdoped portion of the channel.
Preferably, there are shallow counterdoped portion of the channel and source and drain extensions adjacent to the channel between the source region and the drain region.
In accordance with another aspect of this invention, there is provided a charge pump with pass transistors consisting of super Halo asymmetric devices.
Preferably, the asymmetric FET transistor has a source region super halo implant with a shallow counterdoped portion of the channel and source and drain extensions adjacent to the channel between the source region and the drain region; preferably with an abrupt halo contour resulting from a single RTA cycle.
A method of forming an asymmetric MOSFET in a charge pump circuit comprises forming an asymmetric FET transistor of each stage including a semiconductor substrate with a channel, forming a gate electrode stack comprising a silicon oxide layer and a gate electrode formed above the channel, forming a drain region and a source region, the drain region is connected to a drain electrode, the source region is connected to a source electrode, connecting the drain electrode electrically connected through an input node to the gate electrode of the FET transistor and connecting the source electrode of each stage is connected to an output node.
Preferably the method includes forming the asymmetric FET transistor with substantially different forward and reverse threshold voltages, forming a capacitor, with the capacitor of each stage having a first capacitor plate and a second capacitor plate with the first capacitor plate is connected to the source electrode of that stage, and the first and second clocks have a phase differential.